| 摘要 |
PURPOSE: A complementary metal oxide semiconductor(CMOS) device is provided to prevent a hot carrier characteristic and a latch-up characteristic by isolating an n-type MOS from a p-type MOS, and to eliminate junction capacitance and parasitic capacitance by forming an insulator under a source/drain region. CONSTITUTION: An insulation layer is formed on a substrate(31). The first and second sapphire patterns(33a,33b) are formed on the insulation layer at regular intervals. The first and second semiconductor layers are formed on the first and second sapphire patterns. An isolation layer is formed between the first and second sapphire patterns and the first and second semiconductor layers. The first and second trenches are formed in a predetermined depth from the surface of the first and second semiconductor layers. Sidewalls are formed on both side surfaces of the first and second trenches. A gate insulation layer(44) is formed on the first and second semiconductor layers between the sidewalls. The first and second gate electrodes are formed in the first and second trenches on the gate insulation layer. The first conductive impurity region is formed in the first semiconductor layer at both sides of the first gate electrode. The second conductive impurity region is formed in the second semiconductor layer at both sides of the second gate electrode.
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