| 摘要 |
PURPOSE: A test mode entry prohibiting circuit is provided to prohibit a packaged semiconductor integrated circuit from entering a test mode without damaging the semiconductor integrated circuit. CONSTITUTION: A first voltage generator(T01,T4-T6,T8,T09) generates and provides a voltage having a predetermined level to a first node. A reference voltage generator(T02,T07,T10) generates and provides a reference voltage having a predetermined level to a second node. A third voltage generator(T03,T08,T11) generates and provides a voltage having a predetermined level to a third node. A test mode signal generating circuit(30,40,60) outputs a test mode signal in response to a test signal from an input terminal. When a voltage in the first node is higher than the reference voltage or voltages in the first and third nodes are lower than the reference voltage, the test mode signal generating circuit(30,40,60) outputs a test mode signal having a second level to prohibit entering a test mode. |
