发明名称 |
IMAGE PROCESSOR AND IMAGE PROCESSING METHOD |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide an image processor that reduces the required capacity of its memory. SOLUTION: An analyzer 101 detects addresses in which coded data in each stage are stored. Input means i1-i5 transfer coded data in each stage of a block BK 1 to a selector 103 depending on the address information from the analyzer 101. The selector 103 gives the coded data of each stage in the block BK 1 to a Huffman decoder 102. A selector 109 transfers DCT coefficient data in each stage of the block BK 1 from the Huffman decoder 102 to storage areas d1-d5 of a coefficient memory M4. Thus, DCT coefficient data C1-C64 of the block BK 1 are obtained. Inverse quantization, inverse DCT, color space transformation and color number reduction processing are applied to the obtained DCT coefficient data C1-C64 and the resulting data are transferred to an expansion image memory M2. Similarly, expansion image data of blocks BK 2-BK 16 are transferred to the expansion image memory M2.</p> |
申请公布号 |
JP2002084426(A) |
申请公布日期 |
2002.03.22 |
申请号 |
JP20000273752 |
申请日期 |
2000.09.08 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
FUNAHASHI KAZUTOSHI;KURODA MANABU |
分类号 |
H04N19/60;G06T9/00;H03M7/30;H03M7/40;H04N1/41;H04N19/13;H04N19/159;H04N19/162;H04N19/31;H04N19/33;H04N19/42;H04N19/423;H04N19/426;H04N19/46;H04N19/625;H04N19/70;H04N19/91;(IPC1-7):H04N1/41;H04N7/30 |
主分类号 |
H04N19/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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