| 摘要 |
PROBLEM TO BE SOLVED: To improve software error resistance by increasing the storage node capacitance of the memory cell of an SRAM. SOLUTION: In the complete CMOS type SRAM, with which the memory cell is composed of six MISFETs, a pair of local wiring L1 and L2 for connecting the mutual input/output terminals of a CMOS inverter is formed from a high melting point metal silicide layer formed on the upper layer of a first conductive layer comprising respective gate electrodes 6, 10a and 10b of MISFETs Qd1 and Qd2 for driving and MISFETs Qt1 and Qt2 for load of the memory cell and a capacitor is formed by locating a reference voltage line 20, which is formed on the upper layer of such local wiring L1 and L2, so as to overlap it with local wiring L1 and L2. |
