| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic synthesis method which can shorten the period needed to correct logic data and the period needed for layout processing when logic is corrected. SOLUTION: The straight distance from a correcting circuit to a dummy cell is computed (step 104) by inputting logic data 111 of function level having logic corrected, logic information 112 on the dummy cell previously incorporated in logic data of gate level, and information 113 on the arrangement of the dummy cell or another logic cell in a mask layout. Then logic synthesis is carried out (step 105) so as to obtain logic data 116 of gate level used for the layout by using the dummy cell closest to the correcting circuit according to the information obtained through the straight distance computation (step 104). By the above method, the period needed to change the logic data and the period needed for the layout processing can be actualized in a short time.
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