发明名称 |
Process and integrated circuit for a multilevel memory cell with an asymmetric drain |
摘要 |
An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.
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申请公布号 |
US2002034854(A1) |
申请公布日期 |
2002.03.21 |
申请号 |
US20010900778 |
申请日期 |
2001.07.06 |
申请人 |
LU TAO CHENG;CHEN CHUNG JU;LIN HON SUI;WANG MAM TSUNG;LIN CHIN HSI;NI FUL LONG |
发明人 |
LU TAO CHENG;CHEN CHUNG JU;LIN HON SUI;WANG MAM TSUNG;LIN CHIN HSI;NI FUL LONG |
分类号 |
H01L21/8246;H01L27/112;(IPC1-7):H01L21/336;H01L21/425 |
主分类号 |
H01L21/8246 |
代理机构 |
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