Decoder and decoding method

摘要

The present invention provides a decoder with a reduced circuit dimension without adversely affecting the decoding performance of the circuit. The decoder comprises an addition/comparison/selection circuit 60 added to give the log likelihood and adapted to compute a correction term expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood. The addition/comparison/selection circuit 60 stores in ROM 66 the relationship between absolute value data |P-Q| that is a variable of a function and the value obtained by adding the correction term and a predetermined value in the form of a table and turns the absolute value data |P-Q| fed from absolute value computation circuit 65 into an address signal so that the value corresponding to the absolute value data |P-Q| is read out from differentiator 67 as data Z.