| 摘要 |
A pulse width distortion correction logic level converter that converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first and a second converter, wherein the first converter generates a first output signal and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter. The first and second output signals generate a full swing single-ended output signal width that is not sensitive to an absolute delay through the first and second converters.
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