发明名称 |
Processor with cache control |
摘要 |
A CPU system having a built-in cache memory system in which a write-only port for coherence control from the common system side and an access port from the CPU side are isolated through a multi-port configuration of the cache memory system inside CPU. A common memory on the common side too, uses a 2-port system structure with the CPU system in the form of a broadcast type connection form.
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申请公布号 |
US2002035671(A1) |
申请公布日期 |
2002.03.21 |
申请号 |
US20010915381 |
申请日期 |
2001.07.27 |
申请人 |
KAMETANI MASATSUGU;UMEKITA KAZUHIRO;FUNATSU TERUNOBU |
发明人 |
KAMETANI MASATSUGU;UMEKITA KAZUHIRO;FUNATSU TERUNOBU |
分类号 |
G06F12/06;G06F12/08;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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