发明名称 |
Low power scan & delay test method and apparatus |
摘要 |
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
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申请公布号 |
US2002035712(A1) |
申请公布日期 |
2002.03.21 |
申请号 |
US20010955542 |
申请日期 |
2001.09.18 |
申请人 |
WHETSEL LEE D.;GRABER JOEL J. |
发明人 |
WHETSEL LEE D.;GRABER JOEL J. |
分类号 |
G01R31/317;G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/317 |
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地址 |
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