| 摘要 |
The present invention is an apparatus that supports multiple assignment code, comprising a register that may be assigned multiple values, instructions that receive a value and dispatch a result, a first queue that stores the results of an instruction during a pipeline stall, and a second queue that stores the state of the register when an interrupt is taken. The value assigned to a register may be available for processing only after a latency period has passed. The value received by an instruction from a register is the most recent value assigned to the register for which the latency period has passed. The first queue eliminates the need for global stalls in the context of various pipeline implementations. The second queue allows for interruptibility. The present invention further comprises a mode where the software identifies that it does not intend to exploit multiple assignment code. |
