发明名称 |
Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes |
摘要 |
The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode having a bottom layer, an upper interface layer and an intermediate tuning layer disposed between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant dielectric layer disposed between the bottom electrode and the top electrode. The present invention further provides an apparatus and a method for manufacturing high density DRAMs having capacitors having high quality HDC materials and low leakage currents. Another aspect of the present invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention further provides an apparatus and a method for manufacturing capacitors within a high aspect ratio aperture.
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申请公布号 |
US6358810(B1) |
申请公布日期 |
2002.03.19 |
申请号 |
US19980123690 |
申请日期 |
1998.07.28 |
申请人 |
APPLIED MATERIALS, INC. |
发明人 |
DORNFEST CHARLES;EGERMEIER JOHN;KHURANA NITIN |
分类号 |
H01L27/04;H01L21/02;H01L21/316;H01L21/822;H01L21/8242;H01L27/108;(IPC1-7):H01L21/20 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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