Column address decoder and decoding method for controlling column select line enable time

摘要

Disclosed is a column address decoder of a semiconductor memory device for decoding column addresses to enable a corresponding column select line, the column address decoder comprising a column address pre-decoder for latching combinations of the column addresses when a column select line enable signal is in a first level, and outputting the latched result as pre-decoded column addresses when the column select line enable signal is in a second level and a column address main decoder for combining the pre-decoded column addresses and enabling the corresponding column select line among a plurality of column address select lines.