| 摘要 |
In a dual-damascene method for forming an integrated circuit with copper conductors, a fluorinated silicon oxide (SiOF) marker layer is formed between an intermetal silicon dioxide layer and an upper silicon dioxide layer. A plasma etch forms trenches (as sited for future copper conductors) in the upper silicon dioxide layer according to a pattern defined by a photoresist mask. During this trench etch, the spectral characteristics of the plasma are monitored. After the marker layer is exposed and etching of the SiOF begins, an optical spectral detector detect is an enhancement of a spectral signal associated with fluorine ions. This detection is used in determining when to terminate the trench etch. A further photolithographic step results in via apertures. The trenches are then filled with copper. The resulting structure includes marker material in areas protected by the trench etch mask. However, because the dielectric constant of fluorinated silicon oxide (k=3.3-3.6) is lower than that of the main dielectric material, silicon dioxide (k=4), the marker material does not adversely affect the parasitic capacitance of the integrated circuit. Thus, the marker material provides for precise control of trench depth without adversely affecting device performance.
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