发明名称 Dynamic memory with increased access speed and reduced chip area
摘要 A dynamic memory including a first sense amplifier circuit directly connected to a bit line of a memory cell, a second sense amplifier directly connected to a data input/output circuit, a switching circuit connected between the first sense amplifier circuit and the second sense amplifier circuit. In a reading operation, the switching circuit is controlled to separate the first sense amplifier circuit and the second sense amplifier circuit from each other after data is read out from the memory cell, so that the read-out data is amplified by the second sense amplifier circuit and outputted from the second sense amplifier circuit to an external of the memory. On the other hand, the first sense amplifier circuit amplifies the read-out data and writes back the read-out data to the memory cell. In the writing operation, the switching circuit is controlled to interconnect the first sense amplifier circuit and the second sense amplifier circuit to each other, so that data to be written from an external is written into the memory cell through the first and second sense amplifier circuits.
申请公布号 US6359825(B1) 申请公布日期 2002.03.19
申请号 US19990428712 申请日期 1999.10.28
申请人 NEC CORPORATION 发明人 AIMOTO YOSHIHARU;KIMURA TOHRU;TAKEDA KOICHI
分类号 G11C11/409;G11C7/06;G11C7/10;G11C11/406;G11C11/4091;G11C11/4096;(IPC1-7):G11C8/00 主分类号 G11C11/409
代理机构 代理人
主权项
地址