发明名称 |
Coherency protocol for computer cache |
摘要 |
A lower level cache detects when a line of memory has been evicted from a higher level cache. The cache coherency protocol for the lower level cache places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed. Reducing the number of back-invalidate transactions improves the performance of the system.
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申请公布号 |
US6360301(B1) |
申请公布日期 |
2002.03.19 |
申请号 |
US19990290430 |
申请日期 |
1999.04.13 |
申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
GAITHER BLAINE D;RENTSCHLER ERIC M |
分类号 |
G06F12/08;G06F15/16;G06F15/177;(IPC1-7):G06F12/12 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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