发明名称 |
Ultra high density series-connected transistors formed on separate elevational levels |
摘要 |
A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.
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申请公布号 |
US6358828(B1) |
申请公布日期 |
2002.03.19 |
申请号 |
US19980118514 |
申请日期 |
1998.07.17 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
KADOSH DANIEL;GARDNER MARK I. |
分类号 |
H01L27/06;(IPC1-7):H01L21/320;H01L21/476 |
主分类号 |
H01L27/06 |
代理机构 |
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