| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit in which a defective cell can be specified and relieved at the time of a defect of DC current such as defect of standby current or the like and the yield of semiconductor chips can be improved. SOLUTION: At the time of a wafer test performed in manufacturing process, the positive side power source voltage and negative side power source voltage are separately applied to two inverter circuits 8, 9 constituting a memory cell 1 of a SRAM and detection of a defective memory cell in which micro-short- circuit is caused is performed, applying the positive side power source voltage or the negative side power source voltage is cut off by cutting a fuse inserted in wirings for a detected defective memory cell, while a defective memory cell is replaced by a redundant memory cell provided previously in a memory cell array.
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