发明名称 PATTERN FOR EVALUATING BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To design a semiconductor device having a satisfactory breakdown voltage even if mask displacement has occurred in pattern forming. SOLUTION: Breakdown evaluation pattern 60 has a pair of sources 62 (62a, 62b) and a pair of drains (64a, 64b). These sources 62 and drains 64 are covered with an insulation layer not illustrated here. In the insulation layer, contact holes 68 (68a, 68b), 70 (70a, 70b) are formed in positions corresponding to sources 62 and drains 64. In breakdown evaluation pattern 60, these contact holes 68, 70 are arranged symmetrically to the centerline. Through metal wires 72 (72a, 72b), 74 (74a, 74b) arranged on the insulation layer, it is possible to apply voltage between sources 62 and drains 64.
申请公布号 JP2002076085(A) 申请公布日期 2002.03.15
申请号 JP20000254359 申请日期 2000.08.24
申请人 SEIKO EPSON CORP 发明人 TAKIZAWA JUN
分类号 H01L21/66;H01L21/822;H01L27/04;H01L29/78;(IPC1-7):H01L21/66 主分类号 H01L21/66
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