| 摘要 |
<p>PROBLEM TO BE SOLVED: To achieve a common mode input voltage range as wide as a source voltage range, and improve a common mode signal rejection ratio in the common mode input voltage range. SOLUTION: This circuit is so constituted that the first P-channel input stage 51 and the second P-channel input stage 52 are connected to input terminals 21 and 22 in parallel, that the first P-channel input stage 51 is formed of the first and the second low threshold P-channel CMOS transistors 1 and 2 whose threshold voltage is VTP1, that the second P-channel input stage 52 is formed of the third and the fourth low threshold P-channel CMOS transistors 3 and 4 whose threshold voltage is VTP3 (VTP1<VTP3), and that the first and the second P-channel input stages 51 and 52 compensate their operation with each other. Thus it becomes possible to achieve a common mode input voltage range as wide as a source voltage range and to improve a common mode signal rejection ratio in the common mode input voltage range.</p> |
