发明名称 DC TEST DEVICE AND SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To measure respectively output voltage values from a device to be measured for a test pattern for every AD start. SOLUTION: This device is provided with a sequencer 11 outputting successively a start signal, a timing signal, a write-in signal, and a clock signal when an AD start signal is inputted, an ADC 12 measuring an output of a device 3 to be measured to which a test pattern is inputted a start signal is inputted, an operation logic device outputting an output voltage value of ADC, while outputting a result in which the output voltage value is compared with an expected value to a pattern generator as a pass/fail signal, when a timing signal is inputted, an address counter 14 updating an outputted address value when a clock signal is inputted, and a history memory 15 storing a measured value in an address value when a write-in signal is inputted.</p>
申请公布号 JP2002074986(A) 申请公布日期 2002.03.15
申请号 JP20000264029 申请日期 2000.08.31
申请人 ADVANTEST CORP 发明人 TAKEUCHI HIDEO
分类号 G01R31/28;G01R31/3183;G11C16/02;G11C17/00;G11C29/56;(IPC1-7):G11C29/00;G01R31/318 主分类号 G01R31/28
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