| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock signal generating circuit that prevents malfunction of a frequency divider circuit in an abnormal frequency region caused in an unlocked state of a PLL so as to obtain a stable clock frequency. SOLUTION: The clock signal generating circuit consisting of a PLL circuit 104 provided with a phase comparator circuit 101, an integration circuit 102, and a voltage controlled oscillator 103, of a main frequency divider circuit 105, of a sub frequency divider circuit 106, of a switch 107 and of a switch control circuit 108, is brought into a lock state through a loop consisting of the sub frequency divider circuit 106 at start of its operation, then quickly brought into the lock state through a loop consisting of the main frequency divider circuit 105 with an object frequency division rate. |
