| 摘要 |
PROBLEM TO BE SOLVED: To minimize clock skew. SOLUTION: The method comprises a step 2 for recognizing flip flop cells and latch cells where the same clock signal is supplied directly before determining the number of stages of a clock tree and the number of buffer cells or inverter cells interposed as the clock tree, a step 3 for recognizing cells except the flip flop cells and the latch cells where the same clock signal is supplied directly and recognizing the flip flop cells and the latch cells where a clock signal is supplied through the cells, and a step 4 for changing a netlist of a logic level to the netlist of the configuration where buffer cells are interposed in the path through which the same clock signal is supplied directly to the flip flop cells and the latch cells. As a result, the clock signal is supplied to all flip flop cells and latch cells through other cells, and thus the clock skew is minimized.
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