| 摘要 |
PROBLEM TO BE SOLVED: To realize an inverter, a ratio circuit, and a latch circuit where an increase of a load capacity can be restrained and a speedup and low power consumption can be realized by forming the inverter using a MOS transistor, to which short-channels are connected in multiple stages, suppressing a short- channel effect. SOLUTION: The inverter 216 is constituted of transistors 216-1 and 216-2, the inverter 210 is constituted of transistors 210-1 and 210-2 that suppress the short-channel effect respectively and include a plurality of channels to be cascade-connected, input terminals of the inverters are formed by connecting gate electrodes of adjacent channels, and the other gate electrodes are biased to a power supply voltage VDD or a ground potential GND respectively. A data latch is constituted of the inverters 210 and 212 where input/output terminals are alternately connected, an output of the inverter 216 is input into the data latch via a transfer gate 220, and at the time of writing, a logical value zero is written in the data latch by means of a ratio circuit consisting of the transistors 216-2 and 210-1.
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