发明名称 SOFT OUTPUT DECODER AND SOFT OUTPUT DECODING METHOD AND DECODER AND DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To achieve high rate processing in decoding a code having a parallel path while reducing the burden of processing without sacrifice of performance. SOLUTION: A soft output decoding circuit 90 in an element decoder comprises a circuit 157 for distributing a logarithmic likelihood Iγrepresenting the probabilityγdetermined by the output pattern and receiving value of a code logarithmically for each receiving value such that it corresponds to a branch on a trellis depending on the configuration of a code. The Iγdistribution circuit 157 comprises a parallel path processing circuit 2251 for Iβ0 bundling the logarithmic likelihood Iγcorresponding to a parallel path, a parallel path processing circuit 2252 for Iβ1 and a parallel path processing circuit 2253 for Iαwhich are used at the time of decoding a code having a parallel path where the origin of transition has the same state the destination of transition has the same state.
申请公布号 JP2002076936(A) 申请公布日期 2002.03.15
申请号 JP20000263123 申请日期 2000.08.31
申请人 SONY CORP 发明人 MIYAUCHI TOSHIYUKI;YAMAMOTO KOHEI
分类号 G06F11/10;H03M13/25;H03M13/27;H03M13/29;H03M13/39;H03M13/45;(IPC1-7):H03M13/45 主分类号 G06F11/10
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