| 摘要 |
PURPOSE: To provide a TC parallel unit serial connection type ferroelectric memory in which almost constant read-out signal margin can be obtained without depending on a word line position. CONSTITUTION: Cell blocks MCB0, MCB1 constituted by connecting in series plural memory cells MC in which a ferroelectric capacitor C and a cell transistor T are connected in parallel between terminals N1 and N2 is formed along a pair of bit lines BBL, BL. The terminal N1 is connected to the bit lines BBL, BL through block selection transistors BST0, BST1, the terminal N2 is connected to plate lines BPL, PL, a gate of each cell transistor is connected to a word line WL. A sense amplifier circuit 2 is connected to the bit lines BL, BBL. An offset voltage generating circuit 4 compensates the unbalance of a read-out signal caused by a word line position by giving different offset voltage to a bit line in accordance with a selected word line position at the time of reading out data.
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