| 摘要 |
A digital phase detector comprises a frame measurement configuration for counting a first signal clock during every frame of a second signal and for buffering the counted value until it is read by a phase processing unit. In particular this invention allows using size limited clock counters for measurements of unlimited time ranges by combining unlimited number of intermediate samples without accumulating samples granularity errors. In addition to the measurements of the final time ranges, the intermediate samples are available for purposes of digital signal processing. |
