发明名称 Coprocessor circuit architecture, for instance for digital encoding applications
摘要 A coprocessor circuit for processing image data in digital form, having a motion vector controller block for generating, starting from said image data, motion vector values. Such vector values include predictor data and macroblock data relating to a current macroblock of said image data to be estimated, the prediction data and macroblock data being adapted to be stored at respective memory addresses. An address generator block is provided for extracting said respective addresses from said motion vector values. A predictor fetch block for retrieving said predictor data based on respective addresses extracted by said address generator block, a current macroblock fetch and distengine block for retrieving said macroblock data based on respective addresses extracted by said address generator block and for processing said macroblock data according to a given function, all provided, as well as a decision block for collecting said retrieved data as partial results and selecting the best result therefrom.
申请公布号 US2002031179(A1) 申请公布日期 2002.03.14
申请号 US20010819940 申请日期 2001.03.27
申请人 ROVATI FABRIZIO;PAU DANILO;PICCINELLI EMILIANO 发明人 ROVATI FABRIZIO;PAU DANILO;PICCINELLI EMILIANO
分类号 H04N7/26;(IPC1-7):H04N7/12 主分类号 H04N7/26
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