发明名称 |
Multiplication module, multiplicative inverse arithmetic circuit, multiplicative inverse arithmetic control method, apparatus employing multiplicative inverse arithmetic circuit, and cryptographic apparatus and error correction decoder therefor |
摘要 |
A multiplication module, including a first input unit and a second input unit, for multiplying m bits of data in a Galois field GF(2m) (m>=1), includes: first and second power arithmetic units for receiving the first m bits of data from the first input unit; a first multiplication unit for receiving the first m bits of data and the output of the first power arithmetic unit; a second multiplication unit for receiving second m bits of data from the second input unit and the output of the second power arithmetic unit; a selection unit for receiving an output signal from the second multiplication unit and the second m bits of data; and a control unit for outputting a control signal to the first power arithmetic unit, the second arithmetic unit and the selection unit, wherein the first power arithmetic unit receives a first control signal, the second power arithmetic unit receives a second control signal, and the selection unit receives a third control signal, for controlling the output of the selection unit, while the first multiplication unit outputs a first output signal, and the selection unit outputs a second output signal.
|
申请公布号 |
US2002032711(A1) |
申请公布日期 |
2002.03.14 |
申请号 |
US20010990021 |
申请日期 |
2001.11.21 |
申请人 |
MORIOKA SUMIO;KATAYAMA YASUNAO |
发明人 |
MORIOKA SUMIO;KATAYAMA YASUNAO |
分类号 |
G06F7/552;G06F7/72;G09C1/00;H03M13/00;H03M13/15;(IPC1-7):G06F7/00 |
主分类号 |
G06F7/552 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|