发明名称 |
Latching annihilation based logic gate |
摘要 |
The present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.
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申请公布号 |
US2002030512(A1) |
申请公布日期 |
2002.03.14 |
申请号 |
US20010989230 |
申请日期 |
2001.11.20 |
申请人 |
NAFFZIGER SAMUEL D.;DESAI JAYEN J.;RIEDLINGER REID JAMES |
发明人 |
NAFFZIGER SAMUEL D.;DESAI JAYEN J.;RIEDLINGER REID JAMES |
分类号 |
H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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