| 摘要 |
<p>A circuit arrangement, apparatus and method control the transfer of data into an intermediate buffer (28) associated with a split transaction interconnect or bus (16a) by conditioning such transfer on both the amount of free space in the intermediate buffer (28) and whether a data transfer request associated with such transfer of data is ready to be processed at a shared resource (12) that is the target for the data transfer request. As such, whenever data awaiting transfer into the intermediate buffer (28) for at least a certain type of data transfer request is associated with a data transfer request that is not yet ready to be processed by a shared resource (12), data transfer into the intermediate buffer (28) is inhibited, thus freeing the interconnect (16a) to handle other types of pending transfer requests so that such requests may potentially be completed with reduced latency. Data transfer requests, for example, may represent Accelerated Graphics Port (AGP) write transactions to a shared memory (62), whereby control logic (34) for the intermediate buffer (28) is used to store the write data associated with such transactions, and is configured to selectively inhibit the storage of write data associated with an AGP write transaction unless both at least one block of free space (representing the minimum amount of space necessary to start the write transaction) exists in the intermediate buffer (28), and the shared memory (62) is ready to process the transaction.</p> |
