| 摘要 |
PURPOSE: To provide a multi-input data synchronization circuit that synchronously extracts input data from an asynchronous duplex circuit and avoids missing of data on the basis of a slight difference between clock frequencies of both systems. CONSTITUTION: The multi-input data synchronization circuit provided with a data read circuit 32 that synchronously reads input data 10, 20 from FIFO buffer circuits 11, 21 on the basis of a common clock 31, is provided with a counter 14 that counts number of the data on the basis of an A system clock 12, a counter 24 that counts number of the data on the basis of a B system clock 22, and a phase difference detection circuit 30 that receives outputs of both the counters 14, 24 to detect a difference (δten) between arrived points of time of the data 10, 20 of both the systems to the FIFO buffers 11, 21. Furthermore, when the difference (δten) exceeds a half of the data length by one reading of the data read circuit 32, the data arrived earlier are read more by one reading.
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