| 摘要 |
Differential clocks CLKa, CLKb are supplied, and controlled in phase by a phase control circuit. Based on differential clocks CLKa, CLKb that have been controlled in phase by the phase control circuit, a delay-locked loop (DLL) generates 16-phase clocks CLK1 through CLK16, and supplies generated 16-phase clocks CLK1 through CLK16 to phase comparators PD2. A control voltage V2 generated by a phase control signal based on phase difference information (UP/DOWN signal) outputted from phase comparators PD2 is supplied via a feedback loop to the phase control circuit, which uses control voltage V2 for the control of the phase of differential clocks CLKa, CLKb.
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