| 发明名称 |
Method of reducing electrical shorts from the bit line to the cell plate |
| 摘要 |
A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.
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| 申请公布号 |
US2002031875(A1) |
申请公布日期 |
2002.03.14 |
| 申请号 |
US20010943778 |
申请日期 |
2001.08.30 |
| 申请人 |
PAREKH KUNAL R.;DENNISON CHARLES H.;HONEYCUTT JEFFREY W. |
发明人 |
PAREKH KUNAL R.;DENNISON CHARLES H.;HONEYCUTT JEFFREY W. |
| 分类号 |
H01L21/02;H01L21/768;H01L21/8242;(IPC1-7):H01L21/00 |
主分类号 |
H01L21/02 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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