发明名称 CLOCK GENERATING CIRCUIT FOR REGENERATING INPUT DATA AND A METHOD FOR THE USE THEREOF
摘要 <p>The invention relates to a clock generating circuit for regenerating input data in integrated circuits, and to a method for using said clock generating circuit. To this end, a phase-locking loop is used, which comprises a phase detector (6), a control device (7) and an injection-controlled oscillator device (8). At the beginning of the synchronization phase, the injection-controlled oscillator device (8) is excited by received data signals. After a defined time, which corresponds to the time constant of the phase-locking loop, the injection-controlled oscillator device (8) is synchronous, and the connection between the injection-controlled oscillator device and an input terminal connection (1), via which the data is received, is opened.</p>
申请公布号 WO2002021758(A2) 申请公布日期 2002.03.14
申请号 DE2001003520 申请日期 2001.09.11
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