发明名称 |
A SUPER-SELF-ALIGNED TRENCH-GATE DMOS WITH REDUCED ON-RESISTANCE |
摘要 |
A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques. |
申请公布号 |
EP1186023(A1) |
申请公布日期 |
2002.03.13 |
申请号 |
EP20000930123 |
申请日期 |
2000.04.21 |
申请人 |
WILLIAMS, RICHARD K.;GRABOWSKI, WAYNE |
发明人 |
WILLIAMS, RICHARD K.;GRABOWSKI, WAYNE |
分类号 |
H01L29/41;H01L29/78;H01L21/285;H01L21/336;H01L27/02;H01L27/04;H01L27/06;H01L29/06;H01L29/08;H01L29/10;H01L29/40;H01L29/423;H01L29/45;H01L29/739 |
主分类号 |
H01L29/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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