HIGH-SPEED VARIABLE LENGTH DECODER USING PLANE PARTITION

摘要

PURPOSE: A high-speed variable length decoder using plane partition is provided to improve a total speed of a variable length decoder by performing simultaneously a parallel matching process of decoding data and an input process of a decoding code length signal. CONSTITUTION: Two input planes(11) are used for receiving data. The input planes(11) are separated to each other. A programmable logic array(5,5') is connected with a one input plane of the separated input planes(11). A subtracter(19) and an adder(20) are connected with an output terminal of the programmable logic array(5,5'). Code length signals of decoded information of a programmable logic array(5,5') are inputted into each input plane(11) and the subtracter(19), respectively. The remaining bit stream is checked by using the code length signal provided from the programmable logic array(5,5'). A supply control operation of a decoding bit stream is performed by using the code length signal provided from the programmable logic array(5,5').