发明名称 INTERLEAVE ADDRESS GENERATOR
摘要 <p>Memory address generation apparatus 12 generates memory addresses, multiplier 15 reads from memory 14 storing row transposition patterns of a matrix a row transposition pattern value corresponding to the row number output from row counter 11 and calculates an address offset value by multiplying the transposition pattern value of the read row by the number of columns of the matrix, adder 16 reads from memory 13 storing row transposition patterns of the matrix a column transposition pattern value corresponding to the memory address generated by the memory address generation apparatus and generates an interleave address by adding up the transposition pattern value of the read column and the address offset value. &lt;IMAGE&gt;</p>
申请公布号 EP1187339(A1) 申请公布日期 2002.03.13
申请号 EP20010912472 申请日期 2001.03.19
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 IKEDA, TETSUYA;SUZUKI, HIDETOSHI;YAMANAKA, RYUTARO;KURIYAMA, HAJIME
分类号 G06F11/10;G11C8/00;G11C29/00;H03M13/27;H04B14/04;H04L1/00;(IPC1-7):H03M13/27 主分类号 G06F11/10
代理机构 代理人
主权项
地址