发明名称 |
Method and circuitry for supplying clock to internal circuit |
摘要 |
Clock supply circuitry comprises a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal. The clock supply circuitry further includes a PLL output stability detecting circuit. When the clocksupply circuitry is made to return from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which the PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to an internal circuit, the PLL output stability detecting circuit determines whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable. After the PLL output stability detecting circuit determines that the frequency-multiplied clock signal becomes stable, it supplies the frequency-multiplied clock signal from the PLL frequency multiplier as a system clock signal to the internal circuit.
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申请公布号 |
US6356128(B2) |
申请公布日期 |
2002.03.12 |
申请号 |
US20010768238 |
申请日期 |
2001.01.25 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SUGA KENICHI;HONGO KATSUNOBU |
分类号 |
G06F1/04;H03K5/00;H03L7/089;H03L7/095;H03L7/18;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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