| 摘要 |
A glitch removal circuit is disclosed that removes negative glitches from those signals that are provided to circuit elements that are turned-on by negative glitches (e.g., p-channel transistors), and/or removes positive glitches from those signals that are provided to circuit elements that are turned on by positive glitches (e.g., n-channel transistors). The positive glitches need not be removed from those signals that are provided to the circuit elements that are turned-off by positive glitches (e.g., p-channel transistors), and the negative glitches need not be removed from those signals that are provided to circuit elements that are turned-off by negative glitches (e.g., n-channel transistors). An advantage of the present invention is that both positive and negative glitches can be removed in parallel, rather then serially. This can significantly increase the performance of some circuits, and may reduce the amount of glitch removal circuitry required.
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