发明名称 |
Phase locked loop |
摘要 |
A known clock frequency is divided into at least two phases, and the rising and the falling edges of each of the divided signals are counted. The sum total of edges in a given time period is compared to a stored sum of edges during an earlier time period of the same duration. Adjustment to the local clock is made if sufficient differences are detected.
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申请公布号 |
US6356127(B1) |
申请公布日期 |
2002.03.12 |
申请号 |
US20010757554 |
申请日期 |
2001.01.10 |
申请人 |
ADC TELECOMMUNICATIONS, INC. |
发明人 |
KLIPPER JOSHUA;NURKO MOSHE;AGAMI UDI |
分类号 |
H03L7/085;H03L7/181;H04J3/06;H04L7/033;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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