| 摘要 |
A timing circuit for ATE generates an output clock from an input clock and controls output pulse width. The timing circuit includes a differential driver having an input that receives the input clock, and having inverting and non-inverting outputs. The inverting output is coupled to a first phase-locked loop, and the non-inverting output is coupled to a second phase-locked loop. The first and second phase-locked loops respectively generate first and second clocks in response to respective rising and falling edges of the input clock. A combiner circuit converts the first and second clocks into narrow pulse trains, and the pulse trains respectively operate SET and RESET inputs of a SET/RESET flip-flop. The SET/RESET flip-flop generates an output clock having rising edges responsive to rising edges of the input clock, and falling edges responsive to falling edges of the input clock. The timing circuit also includes a frequency divider in feedback path of the phase-locked loops, for establishing a frequency gain of the timing circuit. Pulse width of the output clock is based upon pulse width of the input clock and frequency gain of the timing circuit. To promote timing accuracy, the frequency responses of the phase-locked loops are tailored to selectively filter jitter from the input clock that is uncorrelated with jitter in the ATE, but to pass correlated jitter unattenuated.
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