| 摘要 |
A volatile field programmable gate array (FPGA) having a configurable logical structure portion that is configurable with encrypted configuration data stored external to the FPGA in configuration data memory. On FPGA reconfiguration, for example on power-up, the encrypted configuration data is supplied to an input of the FPGA. In the FPGA, the configuration data is first decrypted by a decryption algorithm embedded in logic, the algorithm using as an operand a decryption key stored in the FPGA in a non-volatile memory, for example EEPROM. The decrypted configuration data is then distributed to the volatile functional portion of the FPGA in a conventional manner. The functional portion may be SRAM. With this design, unauthorized reading of the configuration data of the FPGA by observation of the stream of configuration data transmitted to the FPGA from the external memory, for example during power-up, will only result in encrypted configuration data being obtained. In this way, the design affords enhanced security against the loss of commercially valuable intellectual property and confidential information constituted by the unencrypted configuration data.
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