发明名称 |
Dual bit isolation scheme for flash devices |
摘要 |
The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.
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申请公布号 |
US6355514(B1) |
申请公布日期 |
2002.03.12 |
申请号 |
US20000597358 |
申请日期 |
2000.06.19 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
PHAM TUAN |
分类号 |
H01L21/28;H01L21/336;H01L21/8246;H01L27/115;(IPC1-7):H01L21/824;H01L21/70;H01L21/77;H01L21/82 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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