| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronous circuit designing method, realizing easy circuit design in optimum timing, without depending on processes or the like by using an IP module. SOLUTION: A register transfer language is described, so that a register which is arranged on the same gate stage and is imparted with the same ID number is arranged on the output side of each gate constituting first to fifth gate stages GT1 to GT5 and a signal wire wired on each of the gate stages GT1 to GT5, when performing IP modularizing. Logic composition is performed, without arranging the register for every gate stage. So far as timing is in time as a result of a timing check, the register to be arranged on the gate stage is removed. When timing is not in time, the register is arranged on the gate stage. |
