发明名称 Method and apparatus for preserving data coherency in a double data rate SRAM
摘要 An apparatus and method are provided that preserve data coherency within a DDR SRAM without sacrificing SRAM performance. The presence of a read-following-double-write (RFDW) condition is detected and data is prevented from being output from the SRAM following detection of the RFDW condition until coherent data is available. To detect an RFDW condition, preferably a double write signal is detected during a double write operation, and the double write signal is latched. A read signal also is detected during a read operation and the latched double write signal is compared to the read signal. If both the latched double write signal and the read signal are in a logic state that indicates that each is being performed, the RFDW condition is deemed detected. To prevent data from being pre-maturely output from the SRAM, the off chip driver circuitry of the SRAM preferably is maintained in a tri-state condition and data within a write buffer of the SRAM preferably is blocked until coherent data is available. A circuit for preserving data coherency in DDR SRAM circuitry is provided.
申请公布号 US6356981(B1) 申请公布日期 2002.03.12
申请号 US19990250772 申请日期 1999.02.12
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ROBERTS ALAN L.;WISTORT REID A.
分类号 G11C7/10;G11C11/419;(IPC1-7):G06F12/00 主分类号 G11C7/10
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