| 摘要 |
A computer system or peripheral device includes an arithmetic-logic circuit that provides, for example, in binary parallel format a maximum code from a set of input codes, each input code in binary parallel format. The circuit has minimal propagation delay owing to its expandable architecture which includes: an array of product term generators, a summary term generator, and a selection circuit. Each product term generator primarily includes one AND gate per product term having inputs that combine bits of an input code, the product terms being organized in sets. The summary term generator includes one OR gate for each summary term. The selection circuit includes a multiplexer for each set having data inputs responsive to summary term signals and control inputs responsive to summary term signals of higher significance than the highest summary term on a data input of the multiplexer. In illustrated embodiments, a printer includes an integrated circuit processor of the present invention. The integrated circuit has an interrupt controller having an arithmetic-logic circuit as described above. Other embodiments include shared resource arbitration logic including bus arbitration, sorting circuits, and sensor assay circuits.
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