发明名称 |
Method for making a DRAM cell with deep-trench capacitors and overlying vertical transistors |
摘要 |
A method and structure are achieved for making an array of high-density memory cells for DRAMs. The high density is achieved by forming vertical cylindrical transistors aligned over deep-trench capacitors in a silicon substrate. The method consists of forming a field oxide around and extending inward over a portion of polysilicon trench capacitor electrodes. A gate isolation oxide and an array of word lines are formed aligned over the trench capacitor electrodes, and openings are etched in the word lines to the trench capacitor electrodes. Source contacts are implanted in the trench capacitor electrodes exposed in the openings. A gate oxide for the vertical transistors (FETs) is formed on the sidewalls in the openings, and a P doped polysilicon is formed in the openings for the FET channels. The vertical transistors are then completed by forming a drain implant in the FET channels, and a polysilicon layer is deposited and patterned to form an array of bit lines. The alignment of the vertical transistors over the trench capacitors significantly reduces the memory cell area and increases the memory cell density for future DRAM devices, while providing a cost-effective process.
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申请公布号 |
US6355518(B1) |
申请公布日期 |
2002.03.12 |
申请号 |
US20000655084 |
申请日期 |
2000.09.05 |
申请人 |
PROMOS TECHNOLOGIES, INC. |
发明人 |
WU CHAO-CHUEH;HSIAO CHIA-SHUN |
分类号 |
H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
代理机构 |
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