| 摘要 |
PURPOSE: An output buffer circuit is provided to control tuning-on states of a PMOS transistor and an NMOS transistor by using delay portions. CONSTITUTION: A NAND gate(NAND1) performs a NAND operation for an inverted control signal(CNTR) of an inverter(INV1) and delayed data(DATA) of the first delay portion(1) and outputs a result. A NOR gate(NOR1) performs a NOR operation for the inverted control signal(CNTR) of the inverter(INV1) and delayed data(DATA) of the second delay portion(2) and outputs a result. A PMOS transistor(PM1) and an NMOS transistor(NM1) are connected between a supply power and a ground. The PMOS transistor(PM1) and the NMOS transistor(NM1) are operated and controlled according to an output signal of the NAND gate(NAND1) and an output signal of the NOR gate(NOR1). The first delay portion(1) is formed with four inverter(INV2-INV5), a NAND gate(NAND2), and an inverter(INV6). The second delay portion(2) is formed with four inverters(INV7-INV11) and a NAND gate(NAND3).
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