发明名称 System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
摘要 A cache coherency directory for a shared memory multiprocessor computer system. A data structure is associated with each cacheable memory location, the data structure comprising locations for storing state values indicating an exclusive state, a shared state, an uncached state, a busy state, a busy uncached state, a locked state, and a pending state. The busy state and pending state cooperate to reserve a cache line for future use by a processor while the cache line is currently being used by one or more other processors.
申请公布号 US6356983(B1) 申请公布日期 2002.03.12
申请号 US20000624788 申请日期 2000.07.25
申请人 SRC COMPUTERS, INC. 发明人 PARKS DAVID
分类号 G06F9/52;G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F9/52
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